A Defect Sensitivity Measurement Tool Enabling Comparison of Multilevel Interconnection Strategies

EXTENDED ABSTRACT The introduction of multilevel metalization processes brings new challenges to the design and fabrication of high yielding ICs. As much as 50% of yield loss in digital ICs can be attributed to the metalization stages of fabrication. This can be a particular problem when new process technologies such as multilevel interconnect are being introduced. The EYE tool addresses the problem of design for manufacture of IC layout in multilevel interconnect technologies by enabling the extraction of layout defect sensitivity. The EYE tool can perform a number of operations on integrated circuit mask layout. It supports Boolean (and, or, andnot, exor), polygon bloat/shrink, extra material (figure 1(a)) and pinhole (figure 1(b)) critical area operations. The algorithms used have a time complexity of O(N log N) [1, 2] and